Quick Start

1. Open the emulator in your browser.
2. Select an ISA from the dropdown (default: Intel 8086).
3. Write assembly in the editor, or click Example to load a sample.
4. Press F7 or click Assemble to compile and load into memory.
5. Press F8 or Step to execute one instruction at a time.
6. Press F5 or Run to execute continuously until HLT/BRK.
7. Watch registers, flags, memory, and output update in the tabs on the right.

IDE Guide

Toolbar

Disassembly Interactions

• Click a disassembly line → toggle a breakpoint (red marker)
• Shift+click → set a conditional breakpoint (e.g. CX==0, mem[0x200]==5, AX>10)
• Double-click → run-to-cursor (executes until that instruction is reached)

Editor Autocomplete

Type in the editor to get ISA-aware autocomplete for registers, mnemonics, and labels. Navigate with ↑↓, accept with Tab or Enter, dismiss with Esc.

Languages

Switch language from the Lang dropdown: English, Spanish, German, French, Hindi.

Intel 8086

16-bit x86 processor with segmented memory. The foundation of the x86 architecture that powers most modern PCs. This emulator implements the 8086 instruction set with DOS INT 21h and BIOS INT 10h service subsets.

Registers

General (blue): AX/BX/CX/DX are 16-bit, each split into high/low 8-bit halves (AH/AL, etc). Used for arithmetic, data, pointers.
Index (gray): SI/DI for string operations, BP for stack frames, SP for the stack pointer.
Segment (teal): CS/DS/ES/SS — physical address = segment×16 + offset.
Special (amber): IP = instruction pointer, FLAGS = condition codes.

Flags

Memory Model

1 MiB flat address space. Physical address = segment × 16 + offset. COM programs load at CS:0100h. Programs in this emulator use ORG 100h (COM format).

I/O Model

Text output via INT 21h: AH=01h (read with echo), AH=02h (print char in DL), AH=07h (read no echo), AH=09h (print $-terminated string at DS:DX), AH=4Ch (exit).
Graphics via INT 10h: AH=0Eh (teletype), AH=00h (set video mode, e.g. 13h for 320×200×256).

Interrupts

NMI (non-maskable, vector 02h) and INTR (maskable via IF, device-supplied vector) are available from the header bar. Set up IVT entries at 4×vector with a far pointer (offset + segment).

Instruction Set

Example: Hello World

ORG 100h
MOV DX, OFFSET msg
MOV AH, 09h
INT 21h
MOV AH, 4Ch
INT 21h
msg DB 'Hello, 8086!$'

Intel 8085

8-bit microprocessor with accumulator-centric architecture. The predecessor to the 8086, widely used in embedded systems and education.

Registers

A: 8-bit accumulator — all arithmetic/logic results go here.
B–L: 6 general-purpose 8-bit registers, pairable as BC, DE, HL (16-bit). HL is the primary memory pointer.
SP: Stack pointer. PC: Program counter.

Flags (PSW — A + Flags in one pair)

Memory Model

64 KiB flat address space. Entry at 0000h. Stack grows downward from FFFFh.

I/O Model

Character output via OUT 01h (writes A to the Output tab). All 256 ports are addressable via IN/OUT.

Instruction Set

Interrupts

Hardware interrupts from the header bar:

SID input pin: toggleable from the header. Read via RIM instruction (bit 7 of A).

Example: Output Loop

MVI A, '1'        ; A = 31h
MVI C, 9          ; counter
LOOP: OUT 01h      ; print A
      INR A        ; A++
      DCR C        ; C--
      JNZ LOOP     ; repeat until C=0
HLT

Intel 8051 (MCS-51)

8-bit microcontroller with Special Function Registers (SFRs), bit-addressable RAM, timers, and serial port. Widely used in embedded systems.

Registers

ACC: Accumulator. B: Multiply/divide helper. R0–R7: Register bank (4 banks of 8, selected by PSW.RS0/RS1).
DPTR: 16-bit data pointer (DPH:DPL) for MOVX. SP: Stack pointer (starts at 07h).PC: Program counter.

Memory Map

Key SFRs

Instruction Set

Interrupts

Use the INT0/INT1 header buttons to trigger external interrupts. Type a character in the RX field and click send to inject serial data.

Example: Hello via Serial

MOV A, #'H'
MOV SBUF, A       ; transmit 'H'
JNB TI, $          ; wait for TX complete
CLR TI
MOV A, #'i'
MOV SBUF, A
JNB TI, $
CLR TI
SJMP $

MOS 6502

8-bit processor famous for powering the Apple II, Commodore 64, and NES. Features zero-page fast access, a hardware stack, and decimal mode.

Registers

A: 8-bit accumulator. X, Y: Index registers for addressing and counting.
SP: Stack pointer (8-bit, offset from 0100h — stack page is always 01xxh).
PC: 16-bit program counter. P: Processor status (NV-BDIZC).

Flags (P register)

Memory Map

64 KiB flat address space. Entry at 0000h. Zero page (00–FF) enables faster addressing modes. Stack is fixed at page 1 (0100–01FF).

Addressing Modes

Instruction Set

Interrupts

IRQ (maskable via I flag, vector at FFFEh) and NMI (non-maskable, vector at FFFAh) from the header bar. BRK software interrupt vectors through FFFEh with B flag set.

Example: Sum 1..10

LDA #0              ; accumulator = 0
LDX #10             ; counter
LOOP: CLC
      ADC #X         ; A += X (immediate not valid for ADC, use zero page)
      DEX
      BNE LOOP
BRK                 ; done: A = sum(1..10) = 55

Zilog Z80

8-bit processor, superset of the Intel 8080. Adds IX/IY index registers, shadow registers (A'F'/BC'/DE'/HL'), block transfers, bit manipulation, and multiple interrupt modes.

Registers

Main set: A, F, B, C, D, E, H, L — same as 8080. AF/BC/DE/HL are 16-bit pairs.
IX/IY (purple): 16-bit index registers with displacement addressing (e.g. LD A, (IX+5)).
I: High byte of IM2 interrupt vector table. R: Auto-incrementing memory refresh counter.
SP: Stack pointer. PC: Program counter.

Flags (F register)

Instruction Set

Interrupts

NMI (non-maskable, jumps to 0066h) and INT (maskable via IFF1). Interrupt mode selector in the header:

Example: Hello via OUT

LD A, 'H'
OUT (1), A         ; print 'H'
LD A, 'i'
OUT (1), A         ; print 'i'
HALT

RISC-V RV32I

32-bit RISC processor implementing the base integer ISA (RV32I) with M extension (multiply/divide) and CSR instructions. Uses ECALL semihosting for I/O.

Registers

x0: Always zero. x1–x31: 32 general-purpose 32-bit registers (ABI names in parentheses).
PC: 32-bit program counter. All instructions are 32-bit (4-byte aligned).

Memory Model

Flat 32-bit address space (1 MiB implemented). Little-endian byte ordering. All instructions are exactly 4 bytes (no compressed).

Instruction Formats

Instruction Set

I/O via ECALL Semihosting

Example: Hello World

.text
  LA   a0, msg        ; load address of string
  LI   a7, 64         ; syscall: write
  LI   a0, 1          ; fd = stdout
  LA   a1, msg        ; buffer
  LI   a2, 3          ; length
  ECALL
  LI   a7, 93         ; syscall: exit
  ECALL
msg: .byte 'H','i','\n'

Devices & I/O Peripherals

Simulated hardware accessible via I/O ports. View them in the Devices tab, or pop them out as floating windows.

Debugging Features

Time-Travel Debugging

Every step saves a snapshot. Click Back to undo and restore the previous CPU state (up to 200 steps of history).

Breakpoints

• Click a disassembly line → toggle an unconditional breakpoint
• Shift+click → conditional breakpoint with expression
• Double-click → run-to-cursor

Conditional Breakpoint Expressions

Watch Expressions

In the Watch tab, add register names (e.g. AX) or memory expressions (e.g. [0x200]). Values that change between steps are highlighted in amber.

Snapshot Save/Load

Save downloads a binary snapshot of the entire CPU state (registers, flags, memory, breakpoints, watches). Load restores it deterministically.

Share Links

Share encodes your source code, breakpoints, and watches into a URL. Anyone with the link can open the same program.

Assembly Syntax

All assemblers share: line-oriented, case-insensitive, ; comments, labels (name: or name EQU expr).

Number Formats

Directives

WASM API Reference

The emulator exposes a single Emulator class via wasm-bindgen.

Constructor

const emu = new Emulator("8086"); // "8086"|"8085"|"8051"|"6502"|"Z80"|"rv32"

Core

Debug

I/O

Memory

8051-Specific

8086-Specific

Building from Source

Prerequisites

• Rust with wasm32-unknown-unknown target
• cargo install wasm-pack

# Add WASM target (once)
rustup target add wasm32-unknown-unknown

# Build WASM package
wasm-pack build --target web --out-dir docs/pkg --release --features wasm

# Run native tests
cargo test

# Serve locally
python3 -m http.server -d docs 8000

CLI Runner

cargo run --example run -- examples/hello.asm          # 8086
cargo run --example run -- --isa 8085 examples/hello85.asm
cargo run --example run -- --isa 8051 examples/hello51.asm
cargo run --example run -- --isa z80  examples/helloz80.asm
cargo run --example run -- --isa 6502 examples/hello6502.asm
cargo run --example run -- --isa rv32 examples/hellorv32.asm

Project Structure

multi-cpu-emu/
├── Cargo.toml
├── src/
│   ├── lib.rs          # Emulator enum (6 cores)
│   ├── cpu.rs          # Cpu trait, Mem, Output, FlagSet
│   ├── i8086.rs        # 8086 core
│   ├── i8085.rs        # 8085 core
│   ├── mcs51.rs        # 8051 core
│   ├── m6502.rs        # 6502 core
│   ├── z80.rs          # Z80 core
│   ├── rv32.rs         # RV32I core
│   ├── asm/            # Per-ISA assemblers
│   └── wasm.rs         # wasm-bindgen surface
├── docs/               # Web IDE (GitHub Pages)
│   ├── index.html      # Emulator
│   ├── doc.html        # This page
│   ├── style.css
│   ├── app.js
│   ├── devices.js
│   ├── i18n.js
│   └── screenshots/    # Emulator screenshots
└── examples/run.rs     # Native CLI runner

multi-cpu-emu v0.1.0 · MIT License · GitHub · Written in Rust → WASM